1. Technical Field
This invention relates to devices, and in particular, to devices produced utilizing a silicon oxide glass layer.
2. Art Background Silicon oxide glass layes, e.g., silicon dioxide layers, are frequently utilized in the fabrication of devices such as semiconductor devices. For example, in the fabrication of VLSI semiconductor devices silicon dioxide layers are used as a cap layer for passivation, as a dielectric between two conductors, and as a dielectric to isolate active regions on wafer surfaces.
Not only are silicon oxide glass layers utilized as an integral part of the device strucutre but such layers are also utilized during fabrication and then removed. For example, devices are processed by forming a mask pattern on the upper surface of the device substrate. The mask is formed to have opening that expose underlying device regions to be processed. These masks are typically formed by depositing a resist material, delineating this resist material to have suitable openings, and then performing the required processing.
As device structures become smaller, multilevel resists have been contemplated to achieve the more demanding resolution (See U.S. Pat. No. 4,244,799 dated Jan. 13, 1981 issued to Fraser, Maydan and Moran.) In these configurations, a lower planarizing layer is deposited to provide a relatively planar surface for subsequent resist layers. An intermediary layer is then formed that is resistant to an oxygen reactive ion etching (RIE) process. A final layer is deposited and delineated into the desired patterns. This delineation exposes the intermediary layer which is then fluorine-RIE etched in the configuration defined by the overlying layer. The delineated intermediary layer is, in turn, used as a mask for and oxygen-RIE etch that removes the exposed regions of the underlying layer but does not effect the intermediary layer and thus does not degrade the pattern transfer. The completely processed resist is then utilized for subsequent fabrication procedures.
Generally, silicon oxide glass layers such as the intermediary silicon oxide layer in a multilevel resist, or a silicon oxide glass layer in the device are formed utilizing procedures such as thermal oxidation, sputter deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition or photo-enhanced chemical vapor deposition. These procedures are capable of producing suitable glass layers, e.g., silicon dioxide layers with dielectric constants less than 6, breakdown voltages greater than 4 MV/cm, leakage currents less than 10.sup.-12 amps/cm.sup.2 at 1 MV, and mechanical stresses on silicon of less than 10.sup.10 dynes/cm.sup.2. However, these techniques are relatively costly, produce nearly conformal coatings, and require relatively high processing temperatures, e.g., temperatures about 300 degrees Centrigrade. At processing temperatures greater than 300 degrees Centigrade, undesirable hillock growth is observed on aluminum sputter deposited at 300 degrees Centigrade. (Hillocks are aluminum extrusions as big as or bigger than the design rule of the device.)
Various methods have been suggested for reducing costs associated with silicon oxide glass-layer formations and for producing a relatively planar layer at low temperatures. One proposal involves depositing a silicon-rich glass layer by a spinning technique. Typically, these layers (generally denominated spin-on glasses) are polysiloxanes, i.e., compositions having a high fraction, up to 50 percent, of carbon-silicon bonds. These polymers are dissolved in a suitable solvent spun onto a substrate and then after solvent evaporation and curing (possibly including crosslinking) form a polymer matrix containing silicon in a concentration generally between 15 and 40 weight percent.
Although these spin-on materials are relatively easy to form, their properties have not always been entirely satisfactory. For example, generally the resulting films are porous and thus allow rapid transfer of impurities to the underlying layers. Additionally, these materials at typical processing temperatures outgas substantially, have a breakdown voltage often less than 4 MV/cm, and are not sufficiently resistant to some common fabrication processes, e.g., wet etching with solutions such as aqueous HF.